1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a non-planar transistor having a germanium channel region and a method of manufacturing the same.
2. Description of the Related Art
In order to improve the speed and operation, and reduce the power consumption of a semiconductor device, attempts have been made to increase device density of an integrated circuit by reducing the size of individual transistors of the integrated circuit while maintaining the driving capacity of the transistors. Technology for reducing the size of the semiconductor device is necessary to increase the device density.
A multi-gate transistor in which a gate is formed on a fin shaped silicon body formed using a silicon-on-insulator (SOI) wafer is suggested as a scaling technology of field effect transistors (FETs) to increase the device density of a complementary metal oxide semiconductor (CMOS) structure. Hereafter, the fin shaped silicon body will be referred to as a silicon fin body. The multi-gate transistor using the silicon fin body is used for scaling down the CMOS and provides excellent sub-threshold characteristics and current control capacity without increasing the length of the gate by adopting a complete depletion type SOI structure. In addition, the multi-gate transistor using the silicon fin body efficiently controls a short channel effect (SCE), and thus, the potential of a channel region is not affected by a drain voltage. “35 nm CMOS FinFETs”, VLSI 2002, Fu-Liang Yang et al., U.S. Pat. Nos. 6,413,802, and 6,642,090 provide descriptions of the advantages of the multi-gate transistor using the silicon fin body. These patents are incorporated herein in their entirety by reference.
Another method of scaling the size of a device without affecting the performance of the CMOS device is to improve the mobility of a carrier, that is, an electron or a hole, within a semiconductor material. For example, U.S. Patent Application No. 2003/0102497 A1, incorporated herein in its entirety by reference, discloses a method of optimizing the mobility in a CMOS Fin FET by using various crystal planes.
However, the conventional multi-gate transistor using the silicon fin body limits the material used to compose the channel region to silicon, thus limiting the possibilities for improving the carrier mobility in the channel region.